The Advanced Programmable Switches

APS Networks® provides powerful, Intel® Tofino™-based platforms for open source network innovation. Fully P4 programmable data plane on a powerful hardware base that you can trust. Scalable, Cost-Effective Network Processing on only one platform, replacing a network stack.

APS Networks®: Choice and Control at the Heart of your Network

APS Networks® is about more than just network disaggregation within switches, and software defined networking (SDN). We are using a blend of development skills in hardware, firmware/embedded, OS and application software, to help blow the world of closed networking wide open. We are taking the pieces and putting them back together more securely, more efficiently and, most importantly, doing this as an open, collaborative community together with our customers. Our networking vision includes hardware, open source and programmability, all tailored to our customers‘ business-specific requirements.

Innovative and Open Technology

Our technologies provide the ultimate, stable and supported platform for open network innovation. And our dedicated hardware solutions are built around enabling the latest open technologies to serve vertical industry needs.

Open technology enables hardware and software diversity: reducing risk and lock-in to tardy vendor roadmaps. Users win the freedom to explore the latest advances in networking technology. Network programmability, disaggregation, SDN/NFV and open source software, all become viable options. APS Networks® offers exciting new opportunities to both share in the pace of open innovation, and to engineer your own competitive advantage. And our support and development expertise helps turn this innovation playground into production-ready network environments.

P4 Programming Language

P4 (programming protocol-independent packet processors) is a domain-specific language which is used to specify the packet behavior and unambiguously define the forwarding plane regardless of the underlying hardware, while the program defines the packet headers and the processing logic. It enables the reconfiguration of parsing and the processing, while the hardware (target), which can be an ASIC, an FPGA or a NIC, acts as a compiler, providing information and instructions via match-action tables.

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