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P4 Programming Language

P4 (programming protocol-independent packet processors) is a domain-specific language which is used to unambiguously define the behavior of the forwarding plane regardless of the underlying hardware, with respect to both protocol headers and processing logic. It enables the reconfiguration of parsing and the processing, while the hardware (target), which can be an ASIC, an FPGA or a NIC, acts as a compiler, providing information and instructions via match-action tables.

Although P4 might appear to be a general-purpose programming language, it is not; neither is it a successor of OpenFlow. It can represent any packet forwarding behavior, not only for the Intel® Tofino™ P4-programmable Ethernet switch ASIC, which is also the first hardware switching ASIC that natively supports P4.


P4 was created in 2013 by the P4 Language Consortium, a non-profit organization formed by a group of engineers and researchers from Google, Intel, Microsoft Research, Barefoot Networks, Princeton and Stanford. They required an industry-standard, open programming language, so they developed P4, which is easy to learn and can be used to precisely define how packets are being forwarded within the network infrastructure. Since then, P4 was rapidly adopted by market leaders and gained strong support, in particular among the data center and telecommunications industry. Recently, the P4 Language Consortium was integrated into the Open Networking Foundation, to establish a strong, advancing community.

Data Plane Programming

The P4 programmability enables the user to develop new, customized feautures, reduce complexity by removing unneccessary features and tables, and provides a greater visibility, including diagnostics, telemetry, OAM, any much more. Modularity allowes the user to compose packet forwarding behavior from libraries, and since the forwarding behavior is specified once, it can be compiled to many devices. Protocols are no longer tied to the ASIC, but lifted off into software, as code-specific functionalities deliver precise control over packets.

P4 Applications and Use Cases

P4 can be implemented in an SDN environment to examine the forwarding behavior, associate user-defined keys with actions or add information to the packets. By implementing the protocol P4Runtime, the SDN controller is able to dynamically manage P4 programs throughout the switch pipeline.

P4 enables the user to write complete programs including customized packet forwarding behaviors, and it can serve as a fully operable test environment of an entire network prior to deployment. This is an essential feature for cloud providers, while data centers and service providers benefit from telemetry and measurement. Academic networking research groups are developing new applications based on P4, including load-balancing, consensus protocols and key-value caching.

Load Balancing

Until now, bridging the gap between multi-terabit switches and gigabit servers in today’s demanding network environments has required large numbers of load balancers appliances.

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By employing the Intel® Tofino™ chip with P4 programmability, load balancing can be done inside one single switch, supporting multiple load balancing mechanisms, resilient hashing and flexible allocation of hardware resources.

The distributed architecture and the optimized traffic ensure connection affinity among millions of connections, low latency and terabit speed.

The Tofino™ load balancer enables scaling of specialized web services (SSl accelerators, HTTP compression), security services (intrusion prevention and detection systems, web application firewall), and high-performance video distribution and caching.

In-band Network Telemetry (INT)

INT enables collection of end-to-end, real time state information directly from the data path.

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In this case a P4 program can be used to define the packet header parsing and modifications required for INT. The monitoring function allows the operator to capture and to describe transient issues caused by performance bottlenecks, network failures or configuration errors at line-rate, when precise control over the types of traffic and types of events is required.


Distributed denials of service (DDoS) attacks, such as data breaches, pose a major threat to organizations, government agencies and infrastructural services.

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An Intel® Tofino™ chip enables the devices to detect DDoS attacks among the network infrastructure by either gathering the relevant information via control plane, or estimating and comparing against a threshold directly in the data plane.

The P4 programmability allows highly flexible, scalable and accurate DDoS detection methods and mitigation actions with a minimal consumption of on-chip memory and resources, detecting a DDoS attack in tens of milliseconds.

UHD/4K Video stream processing:

With P4 the uninterrupted transport of UHD/4k videos over long distances is possible. The programmable Intel® Tofino™ chip allows seamless switching of video streams within only one device.

Network Packet Broker:

Traditional network packet brokers are based on ASICs using fixed functions. P4 enables full programmability of the forwarding plane and minimization of outages and performance issues.

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Basic operations, such as packet parsing, match/action operations and packet reassembly, can be described easily with the coding constructs of P4. New protocols can be supported, unused protocols can be removed, and tags for each packet can be created to increase the accessibility of the routing paths.

Offloading Protocols:

The Intel® Tofino™ chip offers the possibility to implement protocols using P4 and run them on the ASIC instead of the CPU, increasing efficiency, control, and network transmission to deliver higher bandwidth.

Advanced Programmable Switches® with P4

P4 is the essential core of our products. The Advanced Programmable Switches® are a series of powerful, agile and versatile open networking switches with a unique architecture, incorporating a combination of the P4-based Intel® Tofino™ chipset and powerful technology to respond to customer-specific use cases.

The devices complete the existing product range on the market and meet business-critical requirements demanding highest levels of reliability, flexibility, security, and performance.

APS Networks® provides the complete service

As APS Networks® is a big supporter of P4 language and open source technology, we employ a professional in-house software development team. Highly skilled staff is acquainted with the latest networking technology, such as P4 and the development of customized SDN controllers.


The Tofino™ P4-programmable Ethernet switch ASIC technology was acquired by Intel from Barefoot Networks in 2019 to help boost the advancement of user-centric solutions in times of growing demand for bandwidth and data availability.

Intel offers The Intel® P4 Suite, a set of capable software tools to develop custom P4 software (Intel® P4 Studio) and to optimize P4 programmable packet processing network devices (Intel® P4 Insight).

Intel® Deep Insight Network Analytics Software brings real-time, fine-grained visibility into your network infrastructure For Network and Server Performance Monitoring. It enables visualization, analysis, tracking and interpretation of every packet’s path, in band at line rate, as well as detection and report of events with nanoseconds accuracy.

Open Access to Intel® Tofino™ Native Architecture

To push forward development and innovation around P4-based networking, Intel opens the Intel® Tofino™ Native Architecture (TNA) and all code can be shared within the community. Intel published the TNA documentation, the TNA files to allow developers share their code, and the Barefoot Runtime Interface (BRI).

You will find all documentation in their GitHub Repository. Read a recent blog post on this major milestone by Sunil Ahluwalia from the Open Networking Foundation (ONF) here.

How to learn programming in P4?

There are multiple ways to get started with P4, regardless of your level of expertise.

To learn P4 it is recommended to have a general understanding of network and telecommunications architecture and protocols, in particular knowledge of the programming languages C and C++, due to its relation to embedded and NOS development, as well as a basic understanding of Python.

  • P4 Language Consortium
    The P4 Language Consortium provides the open source code on their website and recently shared an introductory article from Bruno Rijsman’s blog due to the detailed and precise description of how to take first steps into programming with P4.
  • The P4 Education Working Group
    The P4 Education Working Group frequently hosts P4 Hackathons and workshops all across the globe. These events bring various P4 users of all levels in the open-source community together to share the development of innovative data plane applications, tools and infrastructure.
  • A lot of in-depth information on P4 can also be found online, published by reliable resources, including a remarkable presentation produced by Packet Pushers and put online on YouTube. The presentation explains the program and architectures, the main components of a P4 program and how it functions within the network environment. It illustrates the essential elements of P4 and various use cases of P4Runtime, the control plane interface to P4 for fixed-functions devices. It also provides further valuable web links to online tutorials.
  • Intel® Connectivity Academy
    Since Intel acquired the Intel® Tofino™ Ethernet switch ASIC technology from Barefoot Networks, the world known corporation took over the organization of the professional training courses formerly under the umbrella of Barefoot Academy. The unique P4 trainings provide insights into the relevant technology, such as data plane programming and the next-generation software Intel® P4 Studio, as well as an introduction to Tofino™ architecture, advanced parsing, checksums, and many more. The courses are open to commercial and academic Intel customers. All dates and information about the classes can be found at the Intel® Connectivity Academy.
    You will also find a profound and very comprehensive presentation of Vladmir Gurevich, Principal Engineer at Intel Corporation, on YouTube.